1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor device which has trench gate structure.
2. Description of the Related Art
In a vertical metal-oxide semiconductor field-effect transistor (MOSFET) with striped trench gate structure, avalanche resistance is influenced by a width, a space, and a gross area of a P+ base contact region. The narrower the space of the P+ base contact region is, the more avalanche resistance improves. On the other hand, since a channel region decreases, the on-resistance (Ron) which is one of the performance indices of a vertical MOSFET increases. Hence, it is required to achieve structure of enhancing the avalanche resistance with securing the width of the P+ base contact region (securing the channel region) to reduce the Ron.
An example of a vertical MOSFET which has conventional striped trench gate structure is disclosed in U.S. Pat. No. 6,351,009 B1 (Kocon et al.). With reference to FIGS. 9 to 11, the structure of conventional N channel type vertical MOSFET 300 disclosed in Kocon et al. will be described. FIG. 9 is a schematic plan view showing planar structure of the vertical MOSFET 300 disclosed in Kocon et al. FIG. 10 is a sectional view taken along line 9A-9A′ of FIG. 9, and FIG. 11 is a sectional view taken along line 9B-9B′ of FIG. 9.
As shown in FIGS. 9 to 11, a doped upper layer 302 is arranged on a doped N+ substrate 301. The upper layer 302 includes an N drain region 303 and P wells 305. As shown in FIG. 10, P+ body regions 304 are formed in the upper layer 302. The P+ body regions 304 are mutually isolated by a gate trench 307. On the other hand, as shown in FIG. 11, N+ source regions 306 are formed by ion implantation and diffusion in the upper layer 302. The N+ source regions 306 are isolated by the gate trench 307.
In the gate trench 307, an electroconductive gate material 310 and a dielectric layer 312 are formed. The gate trench 307 is plugged with the electroconductive gate material 310 and dielectric layer 312, and a surface 313 of the dielectric layer 312 and a surface 314 of the P+ body region 304 become substantially coplanar. Then, a metal layer 315 is vapor-deposited on the surface 314. The metal layer 315 forms a contact between the P+ body region 304 and N+ source region 306.
As shown in FIG. 9, the vertical MOSFET 300 includes a plurality of arrays 317 of alternating P+ body regions 304 and N+ source regions 306. Each array 317 is arranged in contact with the gate trench 307, and is isolated from a next array 317. In the each array 317 arranged between gate trenches 307 in FIG. 9, a longitudinal dimension of the N+ source region 306 is formed more widely than that of the P+ body region 304. By this structure, a channel is formed in a plane at which the P well 305 located under the N+ source region 306 is in contact with the gate trench 307, and the Ron which is one of the performance indices is determined. Furthermore, it is possible to narrow a gap between the gate trenches 307 by forming the gate trench 307 so that surface 313 and the surface 314 become substantially coplanar owing to the electroconductive gate material 310 and dielectric layer 312 like this structure. For this reason, it becomes possible to form in high density the channel regions in the same chip area, and to improve the Ron.
In addition, in U.S. Pat. No. 5,998,837 (Williams), an example of a vertical MOSFET which has a conventional striped trench gate structure is disclosed. FIGS. 12 to 15 show the structure of the conventional vertical MOSFET disclosed in Williams. FIGS. 12 and 13 are schematic plan views showing planar structure of vertical MOSFETs 310 and 311 disclosed in Williams. FIG. 14 is a sectional view taken along line 12A-12A′ shown in FIG. 12, or a sectional view taken along line 13A-13A′ shown in FIG. 13. FIG. 15 is a sectional view taken along line 12B-12B′ shown in FIG. 12, or a sectional view taken along line 13B-13B′ shown in FIG. 13. As shown in FIGS. 12 and 13, the vertical MOSFETs 310 and 311 disclosed in Williams have MOSFET cells 81 to 84 and a diode cell 85. Each of the MOSFET cells 81 to 84 has a single N+ source region 88 and a single P+ contact region 87. The diode cell 85 has a deep P+ diffusion dP+ formed in parallel to a gate trench 91.
Nevertheless, the inventors have found out that there are the following issues in these prior arts.
In the conventional structure disclosed in Kocon et al., an optimum value of avalanche resistance exists according to a width and a space of the P+ body region 304. In order to optimize the avalanche resistance, it is necessary to widen the width of the P+ body region 304 and to narrow the space. For this reason, the N+ source regions 306 become narrow, the channel regions decrease, and the Ron increases. Thus, when the Ron is emphasized, avalanche resistance is reduced, and when avalanche resistance is secured, the Ron gets worse, which are in a trade-off relation.
In addition, in the structure disclosed in Williams, the following problems arise. In the structure disclosed in Williams, each width (a space between two adjacent gate trenches 91) y of the MOSFET cells 81 to 84 is restricted by a width of the N+ source region 88, a width of the P+ contact region 87 and a width of the N+ source region 88. For this reason, since it is not possible to narrow the space between the gate trenches 91, there arises a problem that integration is difficult.